GaN-on-SiC semiconductor wafer under inspection lighting
Process Technology

GaN-on-SiC: The Process Stack Behind the Efficiency Numbers

The FA-2400 series efficiency advantage is not a tuning achievement. It is a process architecture decision: gallium nitride on a silicon carbide substrate with a through-wafer copper via thermal path.

Epi Stack

Process Architecture: Layer by Layer

EPI LAYER CROSS-SECTION OHMIC CONTACTS Ti/Al/Ni/Au, rapid thermal annealed SiN PASSIVATION / 100 nm GaN CHANNEL 2DEG ns: 1.4e13 cm-2 Al0.28Ga0.72N BARRIER / 25 nm GaN CHANNEL LAYER / 1.5 um AlN NUCLEATION / 100 nm Fe-DOPED GaN BUFFER (back-barrier) 4H-SiC SUBSTRATE 490 W/mK thermal conductivity 100 mm wafer, on-axis 4 deg miscut THROUGH-WAFER VIA ARRAY Electroplated Cu, 100 um pitch, 0.1 degC/W die attach

The two-dimensional electron gas at the GaN/AlGaN heterojunction carries electrons at mobility above 1800 cm2/V-s, compared to 8500 cm2/V-s in GaAs but at a sheet charge density of 1.4 x 10^13 cm-2, more than double typical GaAs channel density. The combination allows for shorter gate lengths without sacrificing current drive.

Gate length in the FA-2401 is 0.25 um, enabling operation to 18 GHz with adequate gain margin. The FA-2402 and FA-2403 use 0.18 um and 0.15 um respectively for the Ka-band frequency range. The AlGaN barrier composition is tuned per variant to maintain pinch-off voltage uniformity across wafer at each gate dimension.

Breakdown voltage is controlled by the back-barrier Fe-doped GaN isolation layer. Typical BVdgo above 150 V provides drain bias headroom for high-efficiency load line design without reliability compromise.

Thermal Design

Thermal Resistance Path from Gate to Package

Thermal resistance from junction to package case is the FA-2400 differentiating specification for dense phased-array designs. Conventional GaAs flip-chip modules accumulate 25-40 degC/W through die attach alone. The FA-2401 achieves 8.5 degC/W Rth junction-to-case via the through-wafer copper via array and the SiC substrate's inherent thermal conductivity advantage.

The via array uses 100 um pitch electroplated copper columns filling through-wafer laser-drilled holes. Via density is matched to active area heat flux. At 25 W CW, the gate channel temperature rise over package case is 212 degC at conventional GaAs vs 93 degC for the FA-2401. The 119 degC reduction allows either higher sustained power at the same thermal solution, or the same power with a reduced-mass heat spreader.

8.5 degC/W FA-2401 Rth Junction-to-Case (CW, 25 W)
THERMAL RESISTANCE STACK (JUNCTION TO CASE) GaN CHANNEL / 0.3 degC/W SiC 100 um / 1.2 degC/W Cu VIA ARRAY / 0.1 degC/W DIE ATTACH / 2.1 degC/W PACKAGE BASE / 4.8 degC/W TOTAL: 8.5 degC/W FA-2401 GaAs CHANNEL / 0.8 degC/W GaAs 100 um / 4.2 degC/W FLIP-CHIP SOLDER BUMP 28 degC/W PACKAGE BASE / 8.5 degC/W TOTAL: 41.5 degC/W Typical GaAs Module At 25 W CW output: FA-2401 junction temp rise 119 degC lower than GaAs module
Comparison

GaN-on-SiC vs GaAs: Design Target Efficiency at Band

FA-2400 design targets vs published GaAs PHEMT and GaN-on-Si industry data at 14.5 GHz, 21 GHz, and 28 GHz. Typical P1dB drain efficiency under CW conditions at 25 degC package case.

Standard GaAs PHEMT
Drain Eff. at 14.5 GHz P1dB 35-38%
Drain Eff. at 21 GHz P1dB 28-32%
Drain Eff. at 28 GHz P1dB 22-26%
Rth Junction-to-Case 38-48 degC/W
Max junction temp 150 degC
BVdgo typical 12-18 V
Falcomm FA-2400
GaN-on-SiC (FA-2400)
Drain Eff. at 14.5 GHz P1dB >62%
Drain Eff. at 21 GHz P1dB >58%
Drain Eff. at 28 GHz P1dB >52%
Rth Junction-to-Case 8.5-14 degC/W
Max junction temp 250 degC
BVdgo typical >150 V
Standard GaN-on-Si
Drain Eff. at 14.5 GHz P1dB 45-52%
Drain Eff. at 21 GHz P1dB 40-46%
Drain Eff. at 28 GHz P1dB 32-38%
Rth Junction-to-Case 22-35 degC/W
Max junction temp 200 degC
BVdgo typical 80-100 V
Roadmap

Next Capability Milestones

No calendar commitments. These are capability targets the process stack and current characterization data support.

Phase: Q-Band Extension
40-50 GHz band coverage with FA-2404
Extending the FA-2400 series to Q-band using a 0.12 um gate length variant. Process characterization at 40 GHz shows drain efficiency above 44% at P1dB. Qualification reliability data in work.
Phase: MMIC Integration
PA plus driver stage on a single MMIC die
Integrating the driver and output stage in a single GaN-on-SiC MMIC reduces board space and eliminates the inter-stage transmission line insertion loss. Target: FA-2401D, same frequency and power, reduced gain requirement from system LO.
Phase: Linearization Path
DPD-compatible variant for higher-order QAM satellite links
As satellite payloads migrate to higher-order QAM modulation, PA AM-PM linearity becomes the link budget constraint. A predistortion-optimized bias variant with extended AM-PM characterization data is planned for the FA-2402 series.
Phase: Reliability Data
HTOL and HAST qualification dataset for defense and space applications
High-Temperature Operating Life and Highly Accelerated Stress Test datasets for FA-2401 are in progress. This qualification path enables the device for use in defense programs with formal reliability requirements. No schedule committed.